`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    20:29:50 03/13/2014 
// Design Name: 
// Module Name:    rgb 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module rgb(
    input clk_in,
    input empty,
    input [7:0] pixel_data,
	 output reg ready,
    output reg [7:0] red_out,
    output reg [7:0] green_out,
    output reg [7:0] blue_out
    );
	 
//reg ready = 1'b0;
//assign ready = ready;
initial begin
	ready <= 1'b1;
end

reg byte_counter = 1;
//MAKE CHANGES WITH RESPECT TO FIFO EMPTY SIGNAL
always @(posedge clk_in) begin	
		if(empty) begin
			ready <= 1'b0;
		end
		else begin
			ready <= 1'b1;
		end
		
		if(ready) begin
			if(byte_counter) begin
				red_out[7:4] <= pixel_data[7:4];
				green_out[7:4] <= pixel_data[4:0];
			end
			else begin
				blue_out[7:4] <= pixel_data[7:4];
			end
			byte_counter <= ~byte_counter;
		end
end

endmodule
